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| P82B96 Dual bidirectional bus buffer Rev. 06 -- 31 January 2008 Product data sheet 1. General description The P82B96 is a bipolar IC that creates a non-latching, bidirectional, logic interface between the normal I2C-bus and a range of other bus configurations. It can interface I2C-bus logic signals to similar buses having different voltage and current levels. For example, it can interface to the 350 A SMBus, to 3.3 V logic devices, and to 15 V levels and/or low-impedance lines to improve noise immunity on longer bus lengths. It achieves this interface without any restrictions on the normal I2C-bus protocols or clock speed. The IC adds minimal loading to the I2C-bus node, and loadings of the new bus or remote I2C-bus nodes are not transmitted or transformed to the local node. Restrictions on the number of I2C-bus devices in a system, or the physical separation between them, are virtually eliminated. Transmitting SDA and SCL signals via balanced transmission lines (twisted pairs) or with galvanic isolation (opto-coupling) is simple because separate directional Tx and Rx signals are provided. The Tx and Rx signals may be directly connected, without causing latching, to provide an alternative bidirectional signal line with I2C-bus properties. 2. Features I Bidirectional data transfer of I2C-bus signals I Isolates capacitance allowing 400 pF on Sx/Sy side and 4000 pF on Tx/Ty side I Tx/Ty outputs have 60 mA sink capability for driving low-impedance or high capacitive buses I 400 kHz operation over at least 20 meters of wire (see AN10148) I Supply voltage range of 2 V to 15 V with I2C-bus logic levels on Sx/Sy side independent of supply voltage I Splits I2C-bus signal into pairs of forward/reverse Tx/Rx, Ty/Ry signals for interface with opto-electrical isolators and similar devices that need unidirectional input and output signal paths. I Low power supply current I ESD protection exceeds 3500 V HBM per JESD22-A114, 250 V DIP package, 400 V SO package MM per JESD22-A115, and 1000 V CDM per JESD22-C101 I Latch-up free (bipolar process with no latching structures) I Packages offered: DIP8, SO8 and TSSOP8 NXP Semiconductors P82B96 Dual bidirectional bus buffer 3. Applications I Interface between I2C-buses operating at different logic levels (for example, 5 V and 3 V or 15 V) I Interface between I2C-bus and SMBus (350 A) standard I Simple conversion of I2C-bus SDA or SCL signals to multi-drop differential bus hardware, for example, via compatible PCA82C250 I Interfaces with opto-couplers to provide opto-isolation between I2C-bus nodes up to 400 kHz. 4. Ordering information Table 1. Ordering information Package Name P82B96DP P82B96PN P82B96TD P82B96TD/S410 Description Version SOT505-1 SOT97-1 SOT96-1 SOT96-1 TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm DIP8 SO8 SO8 plastic dual in-line package; 8 leads (300 mil) plastic small outline package; 8 leads; body width 3.9 mm plastic small outline package; 8 leads; body width 3.9 mm Type number 4.1 Ordering options Table 2. P82B96DP P82B96PN P82B96TD P82B96TD/S410 Ordering options Topside mark 82B96 P82B96PN P82B96T P82B96T Temperature range -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +125 C Type number P82B96_6 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 -- 31 January 2008 2 of 28 NXP Semiconductors P82B96 Dual bidirectional bus buffer 5. Block diagram VCC (2 V to 15 V) 8 P82B96 Sx (SDA) 1 3 2 Sy (SCL) 7 5 6 4 GND 002aab976 Tx (TxD, SDA) Rx (RxD, SDA) Ty (TxD, SCL) Ry (RxD, SCL) Fig 1. Block diagram of P82B96 6. Pinning information 6.1 Pinning P82B96TD P82B96TD/S410 Sx Rx Tx GND 1 2 8 7 VCC Sy Ry Ty Sx Rx Tx GND 1 2 3 4 002aab978 8 7 6 5 VCC Sy Ry Ty Sx Rx Tx GND 1 2 3 4 002aab979 8 7 VCC Sy Ry Ty P82B96PN 3 4 002aab977 6 5 P82B96DP 6 5 Fig 2. Pin configuration for DIP8 Fig 3. Pin configuration for SO8 Fig 4. Pin configuration for TSSOP8 6.2 Pin description Table 3. Symbol Sx Rx Tx GND Ty Ry Sy VCC Pin description Pin 1 2 3 4 5 6 7 8 Description I2C-bus (SDA or SCL) receive signal transmit signal negative supply transmit signal receive signal I2C-bus (SDA or SCL) positive supply voltage P82B96_6 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 -- 31 January 2008 3 of 28 NXP Semiconductors P82B96 Dual bidirectional bus buffer 7. Functional description Refer to Figure 1 "Block diagram of P82B96". The P82B96 has two identical buffers allowing buffering of both of the I2C-bus (SDA and SCL) signals. Each buffer is made up of two logic signal paths, a forward path from the I2C-bus interface pin which drives the buffered bus, and a reverse signal path from the buffered bus input to drive the I2C-bus interface. Thus these paths are: * sense the voltage state of the I2C-bus pin Sx (or Sy) and transmit this state to the pin Tx (Ty respectively), and * sense the state of the pin Rx (Ry) and pull the I2C-bus pin LOW whenever Rx (Ry) is LOW. The rest of this discussion will address only the `x' side of the buffer; the `y' side is identical. The I2C-bus pin (Sx) is designed to interface with a normal I2C-bus. The logic threshold voltage levels on the I2C-bus are independent of the IC supply VCC. The maximum I2C-bus supply voltage is 15 V and the guaranteed static sink current is 3 mA. The logic level of Rx is determined from the power supply voltage VCC of the chip. Logic LOW is below 42 % of VCC, and logic HIGH is above 58 % of VCC (with a typical switching threshold of half VCC). Tx is an open-collector output without ESD protection diodes to VCC. It may be connected via a pull-up resistor to a supply voltage in excess of VCC, as long as the 15 V rating is not exceeded. It has a larger current sinking capability than a normal I2C-bus device, being able to sink a static current of greater than 30 mA, and typical 100 mA dynamic pull-down capability as well. A logic LOW is only transmitted to Tx when the voltage at the I2C-bus pin (Sx) is below 0.6 V. A logic LOW at Rx will cause the I2C-bus (Sx) to be pulled to a logic LOW level in accordance with I2C-bus requirements (maximum 1.5 V in 5 V applications) but not low enough to be looped back to the Tx output and cause the buffer to latch LOW. The minimum LOW level this chip can achieve on the I2C-bus by a LOW at Rx is typically 0.8 V. If the supply voltage VCC fails, then neither the I2C-bus nor the Tx output will be held LOW. Their open-collector configuration allows them to be pulled up to the rated maximum of 15 V even without VCC present. The input configuration on Sx and Rx also present no loading of external signals even when VCC is not present. The effective input capacitance of any signal pin, measured by its effect on bus rise times, is less than 7 pF for all bus voltages and supply voltages including VCC = 0 V. Remark: Two or more Sx or Sy I/Os must not be interconnected. The P82B96 design does not support this configuration. Bidirectional I2C-bus signals do not allow any direction control pin so, instead, slightly different logic low voltage levels are used at Sx/Sy to avoid latching of this buffer. A `regular I2C-bus LOW' applied at the Rx/Ry of a P82B96 will be propagated to Sx/Sy as a `buffered LOW' with a slightly higher voltage level. If this P82B96_6 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 -- 31 January 2008 4 of 28 NXP Semiconductors P82B96 Dual bidirectional bus buffer special `buffered LOW' is applied to the Sx/Sy of another P82B96 that second P82B96 will not recognize it as a `regular I2C-bus LOW' and will not propagate it to its Tx/Ty output. The Sx/Sy side of P82B96 may not be connected to similar buffers that rely on special logic thresholds for their operation, for example PCA9511, PCA9515, or PCA9518. The Sx/Sy side is only intended for, and compatible with, the normal I2C-bus logic voltage levels of I2C-bus master and slave chips, or even Tx/Rx signals of a second P82B96 if required. The Tx/Rx and Ty/Ry I/O pins use the standard I2C-bus logic voltage levels of all I2C-bus parts. There are no restrictions on the interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s, for example in a star or multipoint configuration with the Tx/Rx and Ty/Ry I/O pins on the common bus and the Sx/Sy side connected to the line card slave devices. For more details see Application Note AN255. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages with respect to pin GND. Symbol VCC VSx VTx VRx In Ptot Tj Tstg Tamb Parameter supply voltage voltage on pin Sx voltage on pin Tx voltage on pin Rx current on any pin total power dissipation junction temperature storage temperature ambient temperature operating operating range P82B96TD/S410 Conditions VCC to GND I2C-bus SDA or SCL buffered output receive input Min -0.3 -0.3 -0.3 -0.3 -40 -55 -40 Max +18 +18 +18 +18 250 300 +125 +125 +85 Unit V V V V mA mW C C C P82B96_6 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 -- 31 January 2008 5 of 28 NXP Semiconductors P82B96 Dual bidirectional bus buffer 9. Characteristics Table 5. Characteristics Tamb = +25 C; voltages are specified with respect to GND with VCC = 5 V, unless otherwise specified. Symbol Parameter Conditions Min Power supply VCC ICC supply voltage supply current operating buses HIGH VCC = 15 V; buses HIGH ICC additional quiescent supply current maximum input/output voltage static output loading on I2C-bus dynamic output sink capability on I2C-bus leakage current on I2C-bus per Tx or Ty LOW 2.0 0.9 1.1 1.7 15 1.8 2.5 3.5 2.0 15 3 4 3.5 V mA mA mA Tamb = +25 C Typ Max Tamb = -40 C to +125 C[1] Min Max Unit Bus pull-up (load) voltages and currents VSx, VSy open-collector; I2C-bus and VRx, VRy = HIGH VSx, VSy = 1.0 V; VRx, VRy = LOW VSx, VSy = 2 V; VRx, VRy = LOW VSx, VSy = 5 V; VRx, VRy = HIGH VSx, VSy = 15 V; VRx, VRy = HIGH VTx, VTy ITx, ITy maximum output voltage open-collector level static output loading on buffered bus dynamic output sink capability, buffered bus leakage current on buffered bus input current from I2C-bus input current from buffered bus leakage current on buffered bus input output logic level LOW on normal I2C-bus temperature coefficient of output LOW levels VTx, VTy = 0.4 V; VSx, VSy = LOW on I2C-bus = 0.4 V VTx, VTy > 1 V; VSx, VSy = LOW on I2C-bus = 0.4 V VTx, VTy = VCC = 15 V; VSx, VSy = HIGH bus LOW; VRx, VRy = HIGH bus LOW; VRx, VRy = 0.4 V VRx, VRy = VCC [2] - - 15 - 15 V ISx, ISy ISx, ISy ISx, ISy 0.2 7 - 18 1 - 3 1 15 30 0.2 7 - 3 10 10 15 30 mA mA A A V mA ITx, ITy 60 100 - 60 - mA ITx, ITy - 1 - - 10 A Input currents ISx, ISy IRx, IRy IRx, IRy -1 -1 1 -10 -10 10 A A A Output logic LOW level VSx, VSy dVSx/dT, dVSy/dT P82B96_6 ISx, ISy = 3 mA ISx, ISy = 0.2 mA ISx, ISy = 0.2 mA [3] [3] [3] 0.8 670 - 0.88 730 -1.8 1.0 790 - (see Figure 6) (see Figure 5) - V mV mV/K (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 -- 31 January 2008 6 of 28 NXP Semiconductors P82B96 Dual bidirectional bus buffer Table 5. Characteristics ...continued Tamb = +25 C; voltages are specified with respect to GND with VCC = 5 V, unless otherwise specified. Symbol Parameter Conditions Min Input logic switching threshold voltages VSx, VSy VSx, VSy dVSx/dT, dVSy/dT VRx, VRy VRx, VRy VRx, VRy VSx, VSy input logic voltage LOW input logic level HIGH threshold temperature coefficient of input thresholds input logic HIGH level input threshold input logic LOW level input/output logic level difference fraction of applied VCC fraction of applied VCC fraction of applied VCC VSx output LOW at 0.2 mA - VSx input HIGH maximum [2] Tamb = +25 C Typ 640 650 -2 0.5VCC 85 Max 600 0.42VCC - Tamb = -40 C to +125 C[1] Min Max Unit on normal I2C-bus on normal I2C-bus [4] [4] 700 0.58VCC 50 (see Figure 7) (see Figure 8) 0.58VCC 50 - mV mV mV/K V V 0.42VCC V mV Logic level threshold difference Thermal resistance Rth(j-pcb) thermal resistance from SOT96-1 (SO8); junction to printed-circuit average lead board temperature at board interface VCC voltage at which all buses are guaranteed to be released temperature coefficient of guaranteed release voltage RTx pull-up = 160 ; no capacitive load; VCC = 5 V 127 K/W Bus release on VCC failure VSx, VSy, VTx, VTy dV/dT 1 (see Figure 9) V - -4 - - - mV/K Buffer response time[5] Tfall delay buffer time delay on VSx to VTx, falling input between VSy to VTy VSx = input switching threshold, and VTx output falling 50 % buffer time delay on Trise delay VSx to VTx, rising input between VSy to VTy VSx = input switching threshold, and VTx output reaching 50 % VCC 70 ns RTx pull-up = 160 ; no capacitive load; VCC = 5 V - 90 - - - ns P82B96_6 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 -- 31 January 2008 7 of 28 NXP Semiconductors P82B96 Dual bidirectional bus buffer Table 5. Characteristics ...continued Tamb = +25 C; voltages are specified with respect to GND with VCC = 5 V, unless otherwise specified. Symbol Parameter Conditions Min Tfall delay VRx to VSx, VRy to VSy Trise delay VRx to VSx, VRy to VSy buffer time delay on falling input between VRx = input switching threshold, and VSx output falling 50 % buffer time delay on rising input between VRx = input switching threshold, and VSx output reaching 50 % VCC input capacitance RSx pull-up = 1500 ; no capacitive load; VCC = 5 V Tamb = +25 C Typ 250 Max Tamb = -40 C to +125 C[1] Min Max ns Unit RSx pull-up = 1500 ; no capacitive load; VCC = 5 V - 270 - - - ns Input capacitance Ci effective input capacitance of any signal pin measured by incremental bus rise times 7 7 pF [1] [2] Limit data for +125 C applies to P82B96TD/S410 version. It is guaranteed by design/characterization, but not by 100 % test. The minimum value requirement for pull-up current, 200 A, guarantees that the minimum value for VSx output LOW will always exceed the minimum VSx input HIGH level to eliminate any possibility of latching. The specified difference is guaranteed by design within any IC. While the tolerances on absolute levels allow a small probability the LOW from one Sx output is recognized by an Sx input of another P82B96, this has no consequences for normal applications. In any design the Sx pins of different ICs should never be linked because the resulting system would be very susceptible to induced noise and would not support all I2C-bus operating modes. The output logic LOW depends on the sink current. For scaling, see Application Note AN255. The input logic threshold is independent of the supply voltage. The fall time of VTx from 5 V to 2.5 V in the test is approximately 15 ns. The fall time of VSx from 5 V to 2.5 V in the test is approximately 50 ns. The rise time of VTx from 0 V to 2.5 V in the test is approximately 20 ns. The rise time of VSx from 0.9 V to 2.5 V in the test is approximately 70 ns. [3] [4] [5] P82B96_6 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 -- 31 January 2008 8 of 28 NXP Semiconductors P82B96 Dual bidirectional bus buffer 1000 VOL (mV) 800 002aac069 1200 VOL (mV) 1000 002aac070 (1) 800 (1) (2) (3) 600 (2) (3) 600 400 -50 -25 0 25 50 75 100 125 Tj (C) 400 -50 -25 0 25 50 75 100 125 Tj (C) VOL at Sx typical and limits over temperature (1) Maximum (2) Typical (3) Minimum VOL at Sx typical and limits over temperature (1) Maximum (2) Typical (3) Minimum Fig 5. VOL as a function of junction temperature (IOL = 0.2 mA) 002aac071 Fig 6. VOL as a function of junction temperature (IOL = 3 mA) 002aac072 1000 VIL(max) (mV) 800 1000 VIH(min) (mV) 800 600 600 400 400 200 -50 -25 0 25 50 75 100 125 Tj (C) 200 -50 -25 0 25 50 75 100 125 Tj (C) VIL(max) at Sx changes over temperature range VIH(min) at Sx changes over temperature range. Fig 7. VIL(max) as a function of junction temperature 1400 VCC(max) (mV) 1200 Fig 8. VIH(min) as a function of junction temperature 002aac075 1000 800 600 400 -50 -25 0 25 50 75 100 125 Tj (C) Fig 9. P82B96_6 VCC(max) that guarantees bus release limit over temperature (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 -- 31 January 2008 9 of 28 NXP Semiconductors P82B96 Dual bidirectional bus buffer 10. Application information Refer to AN460 and AN255 for more application detail. +VCC (2 V to 15 V) +5 V I2C-bus SDA Tx (SDA) Rx (SDA) 1/ R1 'SDA' (new levels) 2 P82B96 002aab986 Fig 10. Interfacing an `I2C' type of bus with different logic levels +VCC +VCC1 R2 R4 R5 +5 V I2C-bus SDA R1 Rx (SDA) Tx (SDA) 1/ R3 I2C-bus SDA 2 P82B96 002aab987 Fig 11. Galvanic isolation of I2C-bus nodes via opto-couplers main enclosure 3.3 V to 5 V 12 V long cables SDA 3.3 V to 5 V 12 V remote control enclosure 12 V 3.3 V to 5 V SDA 3.3 V to 5 V SCL SCL P82B96 P82B96 002aab988 Fig 12. Long distance I2C-bus communications P82B96_6 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 -- 31 January 2008 10 of 28 NXP Semiconductors P82B96 Dual bidirectional bus buffer Figure 13 shows how a master I2C-bus can be protected against short circuits or failures in applications that involve plug and socket connections and long cables that may become damaged. A simple circuit is added to monitor the SDA bus, and if its LOW time exceeds the design value, then the master bus is disconnected. P82B96 will free all its I/Os if its supply is removed, so one option is to connect its VCC to the output of a logic gate from, say, the 74LVC family. The SDA and SCL lines could be timed and VCC disabled via the gate if one or other lines exceeds a design value of `LOW' period as in Figure 28 of AN255. If the supply voltage of logic gates restricts the choice of VCC supply then the low-cost discrete circuit in Figure 13 can be used. If the SDA line is held LOW, the 100 nF capacitor will charge and the Ry input will be pulled towards VCC. When it exceeds 0.5VCC the Ry input will set the Sy input HIGH, which in practice means simply releasing it. In this example the SCL line is made unidirectional by tying the Rx pin to VCC. The state of the buffered SCL line cannot affect the master clock line which is allowed when clock-stretching is not required. It is simple to add an additional transistor or diode to control the Rx input in the same way as Ry when necessary. The +V cable drive can be any voltage up to 15 V and the bus may be run at a lower impedance by selecting pull-up resistors for a static sink current up to 30 mA. VCC1 and VCC2 may be chosen to suit the connected devices. Because DDC uses relatively low speeds (< 100 kHz), the cable length is not restricted to 20 m by the I2C-bus signalling, but it may be limited by the video signalling. +V cable drive VCC1 VCC Rx SCL I2C-bus/DDC master SDA Sy Sx Tx Ry 4.7 k BC 847B 100 nF 100 k +V cable drive VCC2 VCC 3 m to 20 m cables Rx Tx Ry Sx SCL I2C-bus/DDC slave Sy SDA I2C-bus/DDC Ty Ty P82B96 470 k BC 847B 470 k P82B96 GND monitor/flat TV R G B video signals 002aab989 GND PC/TV receiver/decoder box Fig 13. Extending a DDC bus P82B96_6 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 -- 31 January 2008 11 of 28 NXP Semiconductors P82B96 Dual bidirectional bus buffer Figure 14 shows that P82B96 can achieve high clock rates over long cables. While calculating with lumped wiring capacitance yields reasonable approximations to actual timing, even 25 meters of cable is better treated using transmission line theory. Flat ribbon cables connected as shown, with the bus signals on the outer edge, will have a characteristic impedance in the range 100 to 200 . For simplicity they cannot be terminated in their characteristic impedance but a practical compromise is to use the minimum pull-up allowed for P82B96 and place half this termination at each end of the cable. When each pull-up is below 330 , the rising edge waveforms have their first voltage `step' level above the logic threshold at Rx and cable timing calculations can be based on the fast rise/fall times of resistive loading plus simple one-way propagation delays. When the pull-up is larger, but below 750 , the threshold at Rx will be crossed after one signal reflection. So at the sending end it is crossed after 2 times the one-way propagation delay and at the receiving end after 3 times that propagation delay. For flat cables with partial plastic dielectric insulation (by using outer cores) the one-way propagation delays will be about 5 ns per meter. The 10 % to 90 % rise and fall times on the cable will be between 20 ns and 50 ns, so their delay contributions are small. There will be ringing on falling edges that can be damped, if required, by using Schottky diodes as shown. When the Master SCL HIGH and LOW periods can be programmed separately, for example using control registers I2SCLH and I2SCLL of 89LPC932, the timings can allow for bus delays. The LOW period should be programmed to achieve the minimum 1300 ns plus the net delay in the slave's response data signal caused by bus and buffer delays. The longest data delay is the sum of the delay of the falling edge of SCL from master to slave and the delay of the rising edge of SDA from slave data to master. Because the buffer will `stretch' the programmed SCL LOW period, the actual SCL frequency will be lower than calculated from the programmed clock periods. In the example for 25 meters the clock is stretched 400 ns, the falling edge of SCL is delayed 490 ns and the SDA rising edge is delayed 570 ns. The required additional LOW period is (490 ns + 570 ns) = 1060 ns and the I2C-bus specifications already include an allowance for a worst case bus rise time 0 % to 70 % of 425 ns. (The bus rise time can be 300 ns 30 % to 70 %, which means it can be 425 ns 0 % to 70 %. The 25 meter cable delay times as quoted already include all rise and fall times.) Therefore, the microcontroller only needs to be programmed with an additional (1060 ns - 400 ns - 425 ns) = 235 ns, making a total programmed LOW period 1535 ns. The programmed LOW will the be stretched by 400 ns to yield an actual bus LOW time of 1935 ns, which, allowing the minimum HIGH period of 600 ns, yields a cycle period of 2535 ns or 394 kHz. Note that in both the 100 meter and 250 meter examples, the capacitive loading on the I2C-buses at each end is within the maximum allowed Standard mode loading of 400 pF, but exceeds the Fast mode limit. This is an example of a `hybrid' mode because it relies on the response delays of Fast mode parts but uses (allowable) Standard mode bus loadings with rise times that contribute significantly to the system delays. The cables cause large propagation delays, so these systems need to operate well below the 400 kHz limit, but illustrate how they can still exceed the 100 kHz limit provided all parts are capable of Fast mode operation. The fastest example illustrates how the 400 kHz limit can be exceeded, provided masters and slaves have the required timings, namely smaller than the maximum allowed for Fast mode. Many NXP slaves have delays shorter than 600 ns and all Fm+ devices must be < 450 ns. P82B96_6 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 -- 31 January 2008 12 of 28 NXP Semiconductors P82B96 Dual bidirectional bus buffer VCC1 R2 +V cable drive R2 VCC2 VCC VCC R2 Rx Tx Ry R1 R1 R1 R1 Rx Tx Ry R2 SCL I2C-BUS MASTER SDA Sx Sx SCL I2C-BUS SLAVE(S) Sy Ty cable Ty Sy SDA P82B96 C2 C2 P82B96 propagation delay 5 ns/m BAT54A BAT54A C2 C2 GND GND 002aab990 Fig 14. Driving ribbon or flat telephone cables P82B96_6 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 -- 31 January 2008 13 of 28 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 06 -- 31 January 2008 14 of 28 P82B96_6 (c) NXP B.V. 2008. All rights reserved. NXP Semiconductors Table 6. Examples of bus capability Refer to Figure 14. +VCC1 +V cable 12 V 12 V 5V 5V +VCC2 R1 () 750 750 330 330 R2 () 2.2 k 2.2 k 1k 1k C2 (pF) 400 220 220 100 Cable length 250 m 100 m 25 m 3m Cable capacitance n/a (delay based) n/a (delay based) 1 nF 120 pF Cable delay 1.25 s 500 ns 125 ns 15 ns Set master nominal SCL HIGH period LOW period 600 ns 600 ns 600 ns 600 ns 4000 ns 2600 ns 1500 ns 1000 ns Effective bus clock speed 120 kHz 185 kHz 390 kHz 500 kHz Maximum slave response delay Normal spec. 400 kHz parts Normal spec. 400 kHz parts Normal spec. 400 kHz parts 600 ns 5V 5V 3.3 V 3.3 V 5V 5V 3.3 V 3.3 V Dual bidirectional bus buffer P82B96 NXP Semiconductors P82B96 Dual bidirectional bus buffer 10.1 Calculating system delays and bus clock frequency for a Fast mode system local master bus VCCM Rm buffered expansion bus VCCB Rb Rs remote slave bus VCCS MASTER SCL SCL SLAVE Sx P82B96 Tx/Rx Tx/Rx P82B96 Sx I2C-BUS Cm Cb Cs I2C-BUS master bus capacitance buffered bus wiring capacitance slave bus capacitance 002aab991 GND (0 V) Effective delay of SCL at slave: 255 + 17VCCM + (2.5 + 4 x 109 Cb)VCCB + 10VCCS ns. C = F; V = volts. Fig 15. Falling edge of SCL at master is delayed by the buffers and bus fall times local master bus VCCM Rm buffered expansion bus VCCB Rb MASTER SCL Sx P82B96 Tx/Rx Tx/Rx I2C-BUS Cm Cb master bus capacitance GND (0 V) buffered bus wiring capacitance 002aab992 Effective delay of SCL at master: 270 + RmCm + 0.7RbCb ns. C = F; R = . Fig 16. Rising edge of SCL at master is delayed (clock stretch) by buffer and bus rise times P82B96_6 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 -- 31 January 2008 15 of 28 NXP Semiconductors P82B96 Dual bidirectional bus buffer local master bus VCCM Rm buffered expansion bus VCCB Rb Rs remote slave bus VCCS MASTER SDA SDA SLAVE Sx P82B96 Tx/Rx Tx/Rx P82B96 Sx I2C-BUS Cm Cb Cs I2C-BUS master bus capacitance buffered bus wiring capacitance slave bus capacitance 002aab993 GND (0 V) Effective delay of SDA at master = 270 + 0.2RsCs + 0.7 (RbCb + RmCm) ns. C = F; R = . Fig 17. Rising edge of SDA at slave is delayed by the buffers and bus rise times Figure 15, Figure 16, and Figure 17 show the P82B96 used to drive extended bus wiring, with relatively large capacitance, linking two Fast mode I2C-bus nodes. It includes simplified expressions for making the relevant timing calculations for 3.3 V or 5 V operation. Because the buffers and the wiring introduce timing delays, it may be necessary to decrease the nominal SCL frequency below 400 kHz. In most cases the actual bus frequency will be lower than the nominal Master timing due to bit-wise stretching of the clock periods. The delay factors involved in calculation of the allowed bus speed are: A -- The propagation delay of the master signal through the buffers and wiring to the slave. The important delay is that of the falling edge of SCL because this edge `requests' the data or acknowledge from a slave. See Figure 15. B -- The effective stretching of the nominal LOW period of SCL at the master caused by the buffer and bus rise times. See Figure 16. C -- The propagation delay of the slave's response signal through the buffers and wiring back to the master. The important delay is that of a rising edge in the SDA signal. Rising edges are always slower and are therefore delayed by a longer time than falling edges. (The rising edges are limited by the passive pull-up while falling edges are actively driven). See Figure 17. The timing requirement in any I2C-bus system is that a slave's data response (which is provided in response to a falling edge of SCL) must be received at the master before the end of the corresponding LOW period of SCL as appears on the bus wiring at the master. Since all slaves will, as a minimum, satisfy the worst case timing requirements of a 400 kHz part, they must provide their response within the minimum allowed clock LOW period of 1300 ns. Therefore in systems that introduce additional delays it is only necessary to extend that minimum clock LOW period by any `effective' delay of the slave's response. The effective delay of the slaves response equals the total delays in SCL falling P82B96_6 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 -- 31 January 2008 16 of 28 NXP Semiconductors P82B96 Dual bidirectional bus buffer edge from the master reaching the slave (Figure 15) minus the effective delay (stretch) of the SCL rising edge (Figure 16) plus total delays in the slave's response data, carried on SDA, reaching the master (Figure 17). The master microcontroller should be programmed to produce a nominal SCL LOW period = (1300 + A - B + C) ns, and should be programmed to produce the nominal minimum SCL HIGH period of 600 ns. Then a check should be made to ensure the cycle time is not shorter than the minimum 2500 ns. If found necessary, just increase either clock period. Due to clock stretching, the SCL cycle time will always be longer than (600 + 1300 + A + C) ns. Example: The master bus has an RmCm product of 100 ns and VCCM = 5 V. The buffered bus has a capacitance of 1 nF and a pull-up resistor of 160 to 5 V giving an RbCb product of 160 ns. The slave bus also has an RsCs product of 100 ns. The microcontroller LOW period should be programmed to (1300 + 372.5 - 482 + 472) ns, that is 1662.5 ns. Its HIGH period may be programmed to the minimum 600 ns. The nominal microcontroller clock period will be (1662.5 + 600) ns = 2262.5 ns, equivalent to a frequency of 442 kHz. The actual bus clock period, including the 482 ns clock stretch effect, will be below (nominal + stretch) = (2262.5 + 482) ns or 2745 ns, equivalent to an allowable frequency of 364 kHz. 12 V 3.3 V to 5 V Tx SDA 3.3 V to 5 V Ty SCL Sy Ry Sx Rx 12 V twitsted-pair telephone wires, USB, or flat ribbon cables; up to 15 V logic levels, include VCC and GND 12 V 3.3 V 3.3 V P82B96 P82B96 Sx Sy P82B96 Sx Sy P82B96 Sx Sy P82B96 Sy SDA Sx SCL 002aab994 SCL/SDA SCL/SDA SCL/SDA no limit to the number of connected bus devices Fig 18. I2C-bus multipoint application P82B96_6 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 -- 31 January 2008 17 of 28 NXP Semiconductors P82B96 Dual bidirectional bus buffer 14 V Tx 10 002aab995 14 V Rx 10 002aab996 6 Sx 2 6 Sx 2 -2 0 400 800 1200 1600 ns 2000 -2 0 400 800 1200 1600 ns 2000 frequency = 624 kHz ch1 frequency = 624 kHz Fig 19. Propagation Sx to Tx (Sx pull-up to 5 V; Tx pull-up to VCC = 10 V) Fig 20. Propagation Rx to Sx (Sx pull-up to 5 V; Rx pull-up to VCC = 10 V) P82B96_6 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 -- 31 January 2008 18 of 28 NXP Semiconductors P82B96 Dual bidirectional bus buffer 11. Package outline DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-1 D seating plane ME A2 A L A1 c Z e b1 wM (e 1) b2 5 MH b 8 pin 1 index E 1 4 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.14 0.068 0.045 b1 0.53 0.38 0.021 0.015 b2 1.07 0.89 0.042 0.035 c 0.36 0.23 0.014 0.009 D (1) 9.8 9.2 0.39 0.36 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 1.15 0.045 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT97-1 REFERENCES IEC 050G01 JEDEC MO-001 JEITA SC-504-8 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Fig 21. Package outline SOT97-1 (DIP8) P82B96_6 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 -- 31 January 2008 19 of 28 NXP Semiconductors P82B96 Dual bidirectional bus buffer SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE vMA Z 8 5 Q A2 A1 pin 1 index Lp 1 e bp 4 wM L detail X (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012 0.010 0.057 0.004 0.049 0.019 0.0100 0.014 0.0075 0.244 0.039 0.028 0.041 0.228 0.016 0.024 8o o 0 ISSUE DATE 99-12-27 03-02-18 Fig 22. Package outline SOT96-1 (SO8) P82B96_6 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 -- 31 January 2008 20 of 28 NXP Semiconductors P82B96 Dual bidirectional bus buffer TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1 D E A X c y HE vMA Z 8 5 A2 pin 1 index A1 (A3) A Lp L 1 e bp 4 detail X wM 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.45 0.25 c 0.28 0.15 D(1) 3.1 2.9 E(2) 3.1 2.9 e 0.65 HE 5.1 4.7 L 0.94 Lp 0.7 0.4 v 0.1 w 0.1 y 0.1 Z(1) 0.70 0.35 6 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT505-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-04-09 03-02-18 Fig 23. Package outline SOT505-1 (TSSOP8) P82B96_6 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 -- 31 January 2008 21 of 28 NXP Semiconductors P82B96 Dual bidirectional bus buffer 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description". 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 12.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: * Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: * * * * * * Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 12.3 Wave soldering Key characteristics in wave soldering are: * Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave * Solder bath specifications, including temperature and impurities P82B96_6 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 -- 31 January 2008 22 of 28 NXP Semiconductors P82B96 Dual bidirectional bus buffer 12.4 Reflow soldering Key characteristics in reflow soldering are: * Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 24) than a SnPb process, thus reducing the process window * Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board * Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 7 and 8 Table 7. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 8. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 24. P82B96_6 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 -- 31 January 2008 23 of 28 NXP Semiconductors P82B96 Dual bidirectional bus buffer temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 24. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description". 13. Soldering of through-hole mount packages 13.1 Introduction to soldering through-hole mount packages This text gives a very brief insight into wave, dip and manual soldering. Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. 13.2 Soldering by dipping or by solder wave Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 13.3 Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 C and 400 C, contact may be up to 5 seconds. P82B96_6 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 -- 31 January 2008 24 of 28 NXP Semiconductors P82B96 Dual bidirectional bus buffer 13.4 Package related soldering information Table 9. Package CPGA, HCPGA DBS, DIP, HDIP, RDBS, SDIP, SIL PMFP[2] [1] [2] Suitability of through-hole mount IC packages for dipping and wave soldering Soldering method Dipping suitable Wave suitable suitable[1] not suitable For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. For PMFP packages hot bar soldering or manual soldering is suitable. 14. Abbreviations Table 10. Acronym CDM DDC ESD HBM IC I2C-bus MM SMBus Abbreviations Description Charged Device Model Display Data Channel ElectroStatic Discharge Human Body Model Integrated Circuit Inter IC bus Machine Model System Management Bus P82B96_6 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 -- 31 January 2008 25 of 28 NXP Semiconductors P82B96 Dual bidirectional bus buffer 15. Revision history Table 11. P82B96_6 Modifications: Revision history Release date 20080131 Data sheet status Product data sheet Change notice Supersedes P82B96_5 Document ID * * * * * The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Table 5 "Characteristics", sub-section "Bus pull-up (load) voltages and currents", ISx, ISy; leakage current on I2C-bus: change condition "VSx, VSy = 5 V; VRx, VRy = LOW" to "VSx, VSy = 5 V; VRx, VRy = HIGH" Section 10 "Application information", 3rd paragraph on page 12: last 2 sentences re-written. Figure 15 "Falling edge of SCL at master is delayed by the buffers and bus fall times": appended "+ 10 VCCS" to end of equation for effective delay of SCL at slave. Product data sheet Product data Product data Product data Product data 853-2241 29602 of 2003 Feb 28 853-2241 29410 of 2003 Jan 22 853-2241 25758 of 2001 Mar 06 P82B96_4 P82B96_3 P82B96_2 P82B96_1 - P82B96_5 P82B96_4 (9397 750 12932) P82B96_3 (9397 750 11351) P82B96_2 (9397 750 11093) P82B96_1 (9397 750 08122) 20060127 20040329 20030402 20030220 20010306 P82B96_6 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 -- 31 January 2008 26 of 28 NXP Semiconductors P82B96 Dual bidirectional bus buffer 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com P82B96_6 (c) NXP B.V. 2008. All rights reserved. Product data sheet Rev. 06 -- 31 January 2008 27 of 28 NXP Semiconductors P82B96 Dual bidirectional bus buffer 18. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 8 9 10 10.1 11 12 12.1 12.2 12.3 12.4 13 13.1 13.2 13.3 13.4 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Application information. . . . . . . . . . . . . . . . . . 10 Calculating system delays and bus clock frequency for a Fast mode system . . . . . . . . . 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19 Soldering of SMD packages . . . . . . . . . . . . . . 22 Introduction to soldering . . . . . . . . . . . . . . . . . 22 Wave and reflow soldering . . . . . . . . . . . . . . . 22 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 22 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 23 Soldering of through-hole mount packages . 24 Introduction to soldering through-hole mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Soldering by dipping or by solder wave . . . . . 24 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 24 Package related soldering information . . . . . . 25 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 26 Legal information. . . . . . . . . . . . . . . . . . . . . . . 27 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 27 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Contact information. . . . . . . . . . . . . . . . . . . . . 27 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 31 January 2008 Document identifier: P82B96_6 |
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